According to planar complementary metal oxide semiconductor (complementary MOS, or CMOS) technology, field effect transistors of complementary carrier type are formed on a semiconductor substrate, such as a bulk silicon substrate having {100}-type surface orientation. In the process of manufacturing such a semiconductor device, electron channels and hole channels are formed by patterning functional layers formed on the semiconductor substrate, such as layers of doped semiconductor material, metal layers, or oxide layers. The patterned structures are typically aligned with specific crystal directions of the semiconductor substrate, as indicated by a flat or a notch on the periphery of a semiconductor wafer.
When reducing the lateral feature size of semiconductor structures, specifically in the range of sub-quarter micron technologies, the device properties increasingly depend on stress conditions generated during the manufacturing process. This may cause unbalanced modifications in the properties of negative-channel MOS (NMOS) devices and of positive-channel MOS (PMOS) devices.